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HT82V842A
10-Bit 20MSPS CCD Analog Signal Processor
Features
* Operating voltage: 2.7V~3.6V * Low power consumption: 70mW (Typ.) * Power down mode: less than 30mW * Accepts a direct signal input to ADC or PGA at 1.0 * Independent ADC input conversion clock and data
output clock
* Independent CDS and PGA gain control - CDS: -1.94/0/6/12dB - PGA: 0~24dB * Wide gain range: -1.94~36dB * High speed sample and hold circuit: pulse width 11ns
VPP (Typ.)
* CCD signal input level: 1.1 VP-P (Max.) * 10-bit ADC (up to 20MHz) * Black level neutralizer, target setting: 16~127LSB * Built-in serial interface - DNL: 0.6 LSB (Typ.)
(Min.)
* 48-pin LQFP package
General Description
The HT82V842A is a CMOS single-chip signal processing device for CCD area sensors. It consists of a clamp circuit, Correlated Double Sampler (CDS), Programmable Gain Amplifier (PGA), reference voltage generator, black level detection circuit, 20MHz 10-bit A/D converter (ADC), timing generator for internally required pulses, serial interface for internal function control and PGA gain control.
Block Diagram
OBP ADCK BLK CLPCAP A D C L P /C C D C L P CS SCK SDATA MONOUT
T im in g G e n e ra to r
S e r ia l R e g is te r
BandG ap C ir c u it
VRP VCOM VRN
D C C la m p
CCD CLP R E F IN C C D IN CCD A D IN OBCAP OBP DAC C o m p a re B la c k L e v e l R e g is te r AD CLP
CDS
PGA Rough
PGA F in e 0~6dB (0 .0 4 7 d B /S te p ) 1 0 - B it ADC DO 0~DO 9
S /H
-1 .9 4 /0 /6 /1 2 d B 0 /6 /1 2 /1 8 d B
V
DD
V
SS
RESET STBY SHR
SHD
OUTCK
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Pin Assignment
DO0 DO1 DO2 DO3 DO4 VSS VDD DO5 DO6 DO7 DO8 DO9 NC VDD NC VRN VRP VDD VDD VSS VSS VCOM C C D IN R E F IN 2 3 4 5 6 7 8 9 10 11 1
48 47 46 45 44 43 42 41 40 39 38 37
36 35 34 33
H T82V842A 4 8 L Q F P -A
32 31 30 29 28 27
26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 SH SH AD NC VS VD NC NC MO OB AD CL NOUT CAP IN PCAP S D D R CK
OU RE VD VS ST CS SD SC OB NC BL AD K
TCK SET S D
BY ATA K P
C L P /C C D C L P
Pin Description
Pin No. 1, 3, 17~18, 21 NC Pin Name I/O 3/4 3/4 O O 3/4 O I I O I O O I I I I I 3/4 I I I No connection Positive power supply for analog circuit Negative reference voltage for internal ADC Connect to VSS via 0.1mF Positive reference voltage for internal ADC Connect to VSS via 0.1mF Negative power supply for analog circuit Common reference voltage for internal ADC CDS circuit data input CDS circuit reference input Clamp level output Connect to VSS via 0.1mF ADIN signal input Black level integration voltage Connect to VSS via 0.1mF~1mF (by applications) Monitor output of CDS or PGA ADC sampling clock input Reference sampling pulse input Data sampling pulse input Pulse input for ADIN clamp and black calibration control. Clamp control input. Blanking pulse input No connection Black level period pulse input Serial clock input Serial data input Description
2, 6~7, 19, 34, 43 VDD 4 5 8~9, 20, 33, 42 10 11 12 13 14 15 16 22 23 24 25 26 27 28 29 30 VRN VRP VSS VCOM CCDIN REFIN CLPCAP ADIN OBCAP MONOUT ADCK SHR SHD ADCLP/CCDCLP BLK NC OBP SCK SDATA
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Pin No. 31 32 35 36 37~41, 44~48 CS STBY RESET OUTCK DO0~DO9 Pin Name I/O I I I I O Description Serial port chip selection (Active at low) Power down control (Active low) Reset signal (Active low) Clock source for ADC output Digital output from ADC
Absolute Maximum Ratings
Supply Voltage .........................GND-0.3V to GND+6V Input Voltage .............................VSS-0.3V to VDD+0.3V Storage Temperature ...........................-55C to 150C Operating Temperature ..........................-20C to 70C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol VIH VIL IIH IIL IMD IMA ISS VCCDIN Analog Input Range VADIN VCLPCAP tBLKCAL VBLKCAL G (0) G (1) G (2) G (3) Gmin Gmax Gstep ERPA RES Clamp Voltage Black Calibration Time Maximum Calibration Offset Voltage CDS Gain (Set 0 dB) CDS Gain (Set 6.02 dB) CDS Gain (Set 12.04 dB) CDS Gain (Set -1.94 dB) PGA Gain (Minimum Gain) PGA Gain (Maximum Gain) PGA Gain (Gain Step) Total (CDS+PGA) Gain Monotony Resolution 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V Relative gain 3V 3V 3V 3/4 3/4 0 3/4 3/4 0.047 3/4 3/4 0.094 4 10 Absolute gain Relative gain Parameter High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Operation Current at Monitor Disable Supply Current at Monitor Active Power Down Current Test Conditions VDD 3V 3V 3V 3V 3V 3V 3V 3V Conditions 3/4 3/4 VIL=0V VIH=3.0V fS=20MHz fS=20MHz 3/4 CCDIN input, fIN=1MHz ADIN input, fIN=1MHz 3/4 3/4 3/4 Absolute gain Min. 0.7VDD 0 3/4 3/4 3/4 3/4 3/4 3/4 3/4 1.5 3/4 3/4 -2 5.52 11.54 -2.44 -1.2 22.906 Typ. 3/4 3/4 3/4 3/4 23 26 3/4 1.1 1.0 1.7 3/4 200 -1 6.02 12.04 -1.94 -0.2 23.906 Max. VDD 0.3VDD 200 1 3/4 3/4 10 3/4 3/4 1.9 200 3/4 0 6.52 12.04 -1.44 0.8 24.906
Ta=25C Unit V V mA mA mA mA mA VP-P VP-P V Pixel mV dB dB dB dB dB dB dB LSB Bits
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Symbol DNL SN SND VCOM VRP VRN CCAL STCAL Note: Parameter Differential Nonlinearity S/N S/(N+D) ADC Common Voltage VRP Voltage (Positive) VRN Voltage (Negative) ADC Output Black Level Calibration Code Calibration Code Resolution Test Conditions VDD 3V 3V 3V 3V 3V 3V 3V 3V Conditions fS=20MHz 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Min. 3/4 3/4 3/4 1.25 1.55 1.05 16 1 3/4 Typ. 0.6 58 56 1.4 1.65 1.15 3/4 3/4 1 Max. 1.0 3/4 3/4 1.55 1.75 1.25 127 127 3/4 Unit LSB dB dB V V V LSB LSB LSB
Black calibration period is specified when CCAL is from 16 to 127LSB. Although black level codes of 1 to 15 could be set, tBLKCAL is not guaranteed for these codes. VSS=0V, Ta=25C Test Conditions VDD 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V Conditions 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Min. 0.5 50 3/4 3/4 23 23 11 11 3/4 3/4 2 5 1 10 10 0 10 3/4 3/4 3/4 Typ. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 20 20 18 Max. 20 3/4 2 2 3/4 3/4 3/4 3/4 4 4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
A.C. Characteristics
Symbol fS tCYC tR tF tL tH tWR tWD tDR tDD tPSUP tHOLD tSP tSUPE tHOLDE tSUPOC tHOLDOC tDLD tDLE tOL Parameter Conversion Frequency Clock Cycle Time Clock Rising Time Clock Falling Time Clock Low Period Clock High Period SHR Pulse Width SHD Pulse Width SHR Sampling Aperture SHD Sampling Aperture Data Pulse Setup Data Pulse Hold Sampling Pulse Non-overlay Enable Pulse Setup Enable Pulse Hold OUTCK Setup OUTCK Hold 3-state Disable Delay 3-state Disable Delay ADC Output Data Delay
3.0V Active (R) High-Z 3.0V High-Z(R) Active 3.0V 3/4
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Functional Description
CDS (Correlated Double Sampling) Circuit Connect the CCDIN pin to the CCD sensor thru a capacitor. Connect also the REFIN pin to VSS thru a capacitor. The CDS circuit holds the pre-charge voltage of the CCD at SHR pulse and do sampling of the CCD pixel data at SHD pulse. Correlated noise is removed by subtracting the pre-charge voltage from the pixel data level. CDS could choose a gain setting from 0, 6.02, 12 or -1.94dB (Mode 3, register D4 and D5 bits). A CDS gain is controlled by PGA gain. It is recommended to increase the CDS gain then increase the PGA gain to reduce the noise level. Clamp Circuits
* DC clamp
Clamp target (Mode 2 register D5 and D4), input signals (REFIN and CCDIN) to be clamped are selectable. The clamp function can be turned off.
Black Level Cancel Circuit The purpose of a black level cancel circuit is to control the DC level of the PGA input. The ADC output code at an optical black period may correspond to the black level code set up by the register. A black level code of (1 to) 16 to 127 LSB is available (the default is 64 LSB). While the OBP pin is active a black level cancel loop is established. In the loop, a comparison is made between the ADC output code and the black level code, the result controls the voltage of the OBCAP capacitor. Hence, the OBCAP voltage settles gradually and the signal level of the optical black period corresponds to the established value. The following conditions will reset the OBCAP capacitor:
* Set the black level reset register to 1 (Mode 1 regis-
The DC level of the CCDIN/REFIN input is fixed by an internal DC clamp circuit. The DC level of the C-coupled CCD signal at the CDS input is set to CLPCAP by the internal DC clamp circuit. The clamp switches are usually turned on at the black level calibration period. The CLPCAP pin connects to VSS thru a 0.1mF capacitor.
* ADIN signal clamp
ter D1=1).
* Set the RESET pin to low * Power down by STBY pin or register control
Clamp operation can also be used for the ADIN path. The clamp voltage is different from the CCDIN/REFIN signal and it could be turned off by register setting. At ADIN signal to ADC mode, the ADCLP signal controls the clamp circuit. Black level calibration circuit is also controlled by ADCLP at ADIN signal to PGA mode.
* Clamp control
The DC clamping (CCDCLP) is allowed while the OBP pin is low. The black level cancellation is available at ADIN signal to PGA mode. The black level cancellation is available at the ADCLP period in this mode. The clamping function and black level canceling function are done simultaneously.
Clamp current (Mode 2 register D7). Charge current can select normal or fast clamp.
CCD
OB ADCK
E ffe c tiv e P ix e l
B la n k in g
BLK
OBP
CCD CLP
OUTCK
DO
0
~DO
9
D a ta O u tp u t
B la c k C o d e
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B la n k in g CCD E ffe c tiv e P ix e l S ig n a l O p tic a l B la c k P e r io d B la n k in g E ffe c tiv e P ix e l S ig n a l
ADCK
OBP P r e v io u s B la c k Level
R e s u ltin g B la c k C a lib r a tio n L e v e l ( H o ld )
OBCAP
Black Level Calibration Timing High-speed Black Level Cancellation The HT82V842A has a high speed black level cancellation function, which by means of a register setting enhances the settling speed within a fixed period from access to the serial interface. It increases the gain of the setting DAC within a fixed period and in turn increases the charge/discharge current to the OBCAP capacitor. The Mode 3 register D3 to D0 data controls the black level boost function. The default setting is always low
CS tS OBP
UCS
gain (D3~D0=5b0). By setting the register D2~D0, the gain becomes high by 1 to 7 times that of the OBP pulse period after any access to the serial interface. After that period, the gain returns to low. When setting D3 to 1b1, the gain is always high. The CS signal becomes the starting point of the OBP pulse count. The following figure shows the black loop settling gain boost timing chart when the boost control is on (D3=0) and the boost period is set to 3.
tH
CS
C o u n te r 0 B la c k lo o p g a in
1
2
3
3
0
1
2
0
1
2
H ig h g a in
Low
g a in
H ig h g a in
Black Loop Settling Gain Boost Timing Symbol tSUCS tHCS Parameter CS Setup Time CS Hold Time Condition 3/4 3/4 Min. 10 10 Typ. 3/4 3/4 Max. 3/4 3/4 Unit ns ns
Gain Control Circuit The total gain for a CCD input signal covers from -1.94dB to 36dB. The CDS range is 0/6/12/-1.94 dB. The PGA rough is 0/6/12/18dB and ADC fine is 0 to 6dB, 0.047dB/step. The CDS gain is controlled by a 2-bit register and the PGA gain is controlled by a 9-bit register. A/D Converter Circuit The HT82V842A includes one 20MHz 10 bits AD converter. The ADC converts the following signals.
* The signal from the CCDIN input through a CDS and
PGA.
* The signal from the ADIN input through an PGA at the
ADIN mode.
* The signal from the ADIN input at the ADIN mode.
A/D Conversion Range The analog input range of the ADC is determined by the internal reference voltage. The full scale of the ADC is 1.0 VPP.
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A/D Converter Output Code (Mode 1 Register D5=1) The format of an ADC digital output is a straight binary. When in the input zero reference voltage, the output code will be all zero and when the input is a full scale voltage, the output code will be all one. Clock, Pipeline Delay, Digital Data Output Timing The ADCK input is used for an A/D conversion. The ADC input signal is sampled at the falling edge of the ADCK input and 10 bits parallel data is output at the rising edge of the ADCK input after a 5.5 clock of pipeline delay. High-Z Control of ADC Digital Output ADC digital outputs become High-Z under the following conditions:
* Set the ADC output bit to one. (Mode 1 register D2=1) * Set the STBY pin to low * Set the power control bit to one (Mode 1 register
D0=1)
Digital Output Code A/D Input MSB D9 Full Scale : : : : Zero Scale 1 : 1 0 : 0 D8 1 : 0 1 : 0 D7 1 : 0 1 : 0 D6 1 : 0 1 : 0 D5 1 : 0 1 : 0 D4 1 : 0 1 : 0 D3 1 : 0 1 : 0 D2 1 : 0 1 : 0 D1 1 : 0 1 : 0 LSB D0 1 : 0 1 : 0
ADC Data Output (Coding: Straight Binary) Miscellaneous Function (ADC Direct Input, ADIN Mode) The direct input path to the ADC or the PGA is achieved by means of a register setting. The selectable paths are as follows:
* Function disable (default, Mode 1 register D5=0,
Polarity Inversion The following input polarities can be inverted by register setting:
* ADCK (A/D converter sampling clock, Mode 1 register
D6)
* SHR and SHD (CDS sampling clock, Mode 2 register
D4=0)
* ADIN input to the PGA (Mode 1 register D5=0, D4=1) * ADIN input to the PGA (Mode 1 register D5=1,
D3 and D2)
* BLK, OBP, CCDCLP and ADCLP (Mode 2 register D3
and D2) Data Output Clock The ADCK input or the OUTCK input is selectable as an ADC data output clock. Serial Interface Circuit The internal registers of the HT82V842A are controlled by a 3-wire serial interface. The data is a 16-bit length serial data that consists of a 2-bit operation code, 4 bits address and 10 bits data. Each bit is fetched at the rising edge of the CS input. Keep CS to high when not access HT82V842A. It is prohibited to write to a non-defined address. When a data length is below 16 bits, the data is not executed. Registers The HT82V842A has 10 bits7 registers that control the operations. All registers are write only, the serial registers are written by the serial interface.
D4=Dont care) The BLK, SHD and SHR inputs are ignored at the ADIN mode. Power Down Mode The power down mode can be set either by register setting or by the STBY pin. Monitor Output When setting Mode 2 (D1 and D0), the signal from MONOUT is selectable. The alternatives are OFF, CDS output, PGA output or REFIN/CCDIN output. The MONOUT pin gain is fixed to 0dB regardless of the gain control register setting when the CDS output is selected. The MONOUT level becomes VCOM at zero reference level. The signals are output in reverse for the CCD input.
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R/W W W W W W Address A3 0 0 0 0 0 A2 0 0 0 0 1 A1 0 0 1 1 0 A0 0 1 0 1 0 Register Name Mode 1 Mode 2 Mode 3/CDS gain PGA gain Black level Function Description DOUT timing control/OUTCK polarity/ADCK polarity/ADIN connection/ADC output/Black level reset/Power down Clamp current/ADIN clamp/Clamp target/S/H, enable logic/Monitor selection CDS gain control/Black loop gain boost/Boost period PGA gain ADC code at black level (1 LSB step) Register Map Register Bit Assignment D9 Mode 1 Default Functions DOUT timing control OUTCK polarity ADCK polarity ADIN connection Reserved ADC output Black level reset Power down Mode 2 Default Functions Clamp current ADIN clamp Clamp target S/H, enable logic Monitor selection Mode 3 Default Functions CDS gain control Black loop gain boost Boost period PGA Gain Default Functions PGA gain Black Level Default Functions Black level -----------------------------------------------------------------------X X X 1 0 0 0 0 0 0 ---------------------------------------------------------------------------------------------------X 0 0 0 0 0 0 0 0 0 -----O --------------------------X X X X 0 0 0 0 0 0 O O ---------------X X 0 0 0 0 0 0 0 0 O O O -----O O O O X 0 0 0 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 D1 D0
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Register Operations Control D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Mode 1 DOUT timing control OUTCK polarity ADCK polarity 0 1 0 1 0 1 0 ADIN connection 0 1 Reserved ADC output Black level reset Power down Mode 2 Clamp current ADIN clamp 0 1 0 1 0 Clamp target 0 1 1 0 1 0 1 0 S/H, enable logic 0 1 1 0 1 0 1 0 Monitor selection 0 1 1 Mode 3 0 CDS gain control 0 1 1 Black loop gain boost 0 1 0 1 0 1 CDS gain=odB CDS gain=6.02dB CDS gain=12.04dB CDS gain=-1.94dB Boost control on Always high gain Normal clamp 50mA Fast clamp 100mA Clamp operation active for ADIN No clamp for ADIN Normal mode, clamp both REFIN and CCDIN Clamp REFIN only Clamp CCDIN only Clamp off Normal operation as timing chart S/H control polarity inversion Enable control polarity inversion Both of S/H and enable inversion 0 Monitor off 1 CDS signal to monitor 0 PGA output monitor 1 Output REFIN and CCDIN 0 1 x 0 1 0 1 0 1 DOUT synchronizes to ADCK DOUT synchronizes to OUTCK DOUT changes at OUTCK rising edge DOUT changes at OUTCK falling edge Normal operation as timing chart ADCK clock inversion ADIN function OFF ADIN signal to PGA ADIN signal to ADC Reserved Reserved Normal operation, ADC data output ADC output high-Z, or logic of STBY Normal operation Black level reset, or logic of RESET 0 Normal operation 1 Power down, or logic of STBY Operations
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Control D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 Boost period 0 0 0 0 0 Control D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 0 0 0 0 1 1 0 0 1 0 0 PGA gain 0 1 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 00 11 02 13 04 0 62 1 63 0 64 1 65 1 127 0 128 1 129 0 192 1 255 0 256 1 257 0 320 1 383 0 384 1 385 0 448 0 510 1 511 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 Always low gain 1 High gain for 1 OBP pulse 0 High gain for 2 OBP pulse 1 High gain for 3 OBP pulse 0 High gain for 4 OBP pulse 1 High gain for 5 OBP pulse 0 High gain for 6 OBP pulse 1 High gain for 7 OBP pulse Operations
Decimal 0 1 2 3 4 3E 3F 40 41 7F 80 81 C0 FF 100 101 140 17F 180 181 1C0 1FE 1FF
HEX
PGA Gain (dB) 0 0.046 0.093 0.142 0.187 2.915 2.962 3.011 3.056 5.972 6.021 6.058 9.031 11.994 12.041 12.087 15.05 18.14 18.061 18.108 21.071 23.987 24.032
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Operation, ADC Code D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 Black level 0 1 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 Decimal Black Code HEX Forbidden 1 F 10 11 12 13 20 40 7C 7D 7E 7F
0 Forbidden 11 1 15 0 16 1 17 0 18 1 19 0 32 0 64 0 124 1 125 0 126 1 127
Timing Diagrams
tD
R
tD
D
CCD R e fe r e n c e S a m p lin g D a ta S a m p lin g SHR tW
D
tW
R
tP
SUP
tS
P
SHD tC ADCK BL OB CCDCL ADCL P K P P tH
O LDE YC
tH
O LD
tH tH tS
tL
tS
UPE
O LDC
UPOC
OUTCK tO
L
DO
0
~DO
9
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AD Conversion Timing (at ADIN (ADC) Input Mode 1 Register D5=1)
0 .7 A V ADCK 0 .3 A V F a llin g E d g e A D C In p u t N S a m p lin g P o in t 0 .7 A V OUTCK 0 .3 A V tD
L DD DD DD DD
N+1
N+4
N+5
N+6
D ig ita l O u tp u t
N -6
N -5
N -2
N -1 N
ADC Direct Input Chart
ADCK R is in g E d g e N N+1
ADCK
tH OUTCK
O LDC
tS
UPOC
A D C K In p u t
S a m p lin g P o in t
ADCK Inversion Chart
OUTCK Timing Chart
These figures are shown when the Mode 1 D8 bit is set to 1, and an external clock is input to the OUTCK pin. When setting D8 bit to 0, the ADCK is used as OUTCK. Note: At default condition in ADIN mode, data are sampled at the falling edge of the ADCK clock, and are output at the rising edge of the OUTCK clock. Set the ADCK polarity register to 1 when the data are sampled and are output at the falling edge of the ADCK clock. The diagram on the upper portion of this page shows the default timing and the lower left figure shows the inverted timing. Delay from data sampling to data output ADCK normal: At Mode 1 register D6=0; 5.5 clk delay ADCK inversion: At Mode 1 register D6=1; 6.0 clk delay In ADIN input mode, the above mentioned register setting is available. At ADIN (PGA) input Mode 1 register D5=0 and D4=1, digital data output is delayed by 2 clks. ADCK Clock Waveform
tH
0 .7 V
DD
0 .3 V
DD
tR
tF tC
YC
tL
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Control Interface Timing Symbol SCYC SLO SHI SSU SH SR SF SNUM Parameter SCK Clock Frequency SCK Clock Low Level Width SCK Clock High Level Width Data Setup Time Period Data hold Time Period SCK, CS Rising Time Period SCK, CS Falling Time Period Number of Serial Data Test Conditions VDD 3.0V 3.0V 3.0V 3.0V 3.0V Conditions 3/4 3/4 3/4 3/4 3/4 Min. 3/4 40 40 20 20 3/4 3/4 3/4 Typ. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 16 VSS=0V, Ta=25C) Max. 10 3/4 3/4 3/4 3/4 6 6 3/4
50%
S
SU
Unit MHz ns ns ns ns ns ns pcs
3.0V 30%(R)70% 3.0V 70%(R)30% 3.0V 3/4
CS
S
CYC
V
DD
S
H HI
S
LO
S
SCK
S S
H
50%
V
DD
SU
SDATA
O0
O1
A 0 ...
S
NUM
D8
D9
50%
V
DD
Serial I/F Timing Chart Data Output Sequence
CCD 0 SHR SHD 1 2 3 4 5 6 7 8
ADCK OUTCK BLK
DO
0
~DO
9
B la c k L e v e l C o d e
0
1 2
3
Pixel Data Readout Sequence (1): Start of Conversion
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CCD (N -1 ) SHR SHD N
ADCK OUTCK BLK
DO
0
~DO
9
N -8
N -7
N -6
N -5
N -4
N -3
N -2
N -1
N
B la c k L e v e l C o d e
Pixel Data Readout Sequence (2): End of Conversion
Clock Timing Variations by Register Setting Clock timing variations when it is inverted by register settings.
* No inversion
Mode 1 register D6=0, Mode 2 register D2=0; Default
CCD
SHR SHD ADCK OUTCK
DO
0
~DO
9
Pulse Control (Default: No Inversion)
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* ADCK inversion
Mode 1 register D6=1, Mode 2 register D2=0
CCD
SHR SHD ADCK OUTCK
DO
0
~DO
9
Pulse Control (ADCK Inversion)
* SHR & SHD inversion
Mode 1 register D6=0, Mode 2 register D2=1
CCD
SHR SHD ADCK OUTCK
DO
0
~DO
9
Pulse Control (SHR & SHD Inversion)
* ADCK, SHR & SHD inversion
Mode 1 register D6=1, Mode 2 register D2=1
CCD
SHR SHD ADCK OUTCK
DO
0
~DO
9
Pulse Control (ADCK, SHR & SHD Inversion) Rev. 1.00 15 January 2, 2006
HT82V842A
Application Circuits
0 .1 m F P o w e r In 48 DO9 47 46 45 44 43 42 41 40 39 38 37
VDD DO5
DO8
DO7
DO6
DO4 VSS
DO3
DO2
DO1
DO0
P o w e r In 1 2 0 .1 m F 3 4 5 0 .1 m F 10mF 0 .1 m F 6 7 0 .1 m F 8 9 10 0 .1 m F 0 .1 m F CCD 0 .1 m F 11 12
NC VDD NC VRN VRP VDD VDD VSS VSS VCOM C C D IN R E F IN MONOUT CLPC AP 13 0 .1 m F OBCAP 0 .1 m F 15 A D IN
OUTCK RESET VDD VSS STBY CS SDATA SCK OBP NC BLK A D C L P /C C D C L P SHD SHR ADCK NC VDD VSS NC NC * 0 .1 m F
36 35 34 33 32 31 30 29 28 27 26 25
P o w e r In 0 .1 m F
H T82V842A
Note:
* Pin 18 can also connect to ground with a 4.7kW resistor. ** The capacitor connects to OBCAP pin maybe need adjust by users applications from 0.1mF~1mF typically.
14
0* * . 1 m F
16
17
P o w e r In
18
19
20
21
22
23
24
Rev. 1.00
16
January 2, 2006
HT82V842A
Package Information
48-pin LQFP (77) Outline Dimensions
C D 36 25 G H
I 37 24
F A B E 48 13 K 1 12 a J
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 8.90 6.90 8.90 6.90 3/4 3/4 1.35 3/4 3/4 0.45 0.10 0 Nom. 3/4 3/4 3/4 3/4 0.50 0.20 3/4 3/4 0.10 3/4 3/4 3/4 Max. 9.10 7.10 9.10 7.10 3/4 3/4 1.45 1.60 3/4 0.75 0.20 7
Rev. 1.00
17
January 2, 2006
HT82V842A
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 0755-8616-9908, 8616-9308 Fax: 0755-8616-9533 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 028-6653-6590 Fax: 028-6653-6591 Holmate Semiconductor, Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright O 2006 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
18
January 2, 2006

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